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MCP6S21/2/6/8
1.1
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
V OUT (V)
The ideal PGA output voltage (V OUT ) is:
V DD
EQUATION
V O_ideal = GV IN
V REF = V SS = 0V
V DD -0.3
V 2
where: G is the nominal gain
(see Figure 1-7). This equation holds when there are
no gain or offset errors and when the V REF pin is tied to
a low impedance source (<< 0.1 ? ) at ground potential
(V SS = 0V).
0.3
0
V 1
V IN (V)
1.1.2 LINEAR MODEL
The PGA’s linear region of operation, including offset
0
0.3
G
V DD - 0.3 V DD
G G
and gain errors, is modeled by the line V O_linear , shown
in Figure 1-7.
FIGURE 1-7: Output Voltage Model with
the standard condition V REF = V SS = 0V.
EQUATION
1.1.3
OUTPUT NON-LINEARITY
V O_linear = G ( 1 + g E ) ( V IN – 0.3V + V OS ) + 0.3V
V REF = V SS = 0V
Figure 1-8 shows the Integral Non-Linearity (INL) of the
output voltage.
The endpoints of this line are at V O_ideal = 0.3V and
V DD -0.3V. The gain and offset specifications referred to
in the electrical specifications are related to Figure 1-7,
EQUATION
INL = V OUT – V O_linear
as follows:
The output non-linearity specification in the electrical
EQUATION
specifications is related to Figure 1-8 by:
V 2 – V 1
G ( V DD – 0.6V )
V 1
V OS = -------------------------
V ONL = ---------------------------------
? G ? ? T A = ----------
g E = 100% --------------------------------------
G = +1
G ( 1 + g E )
? g E
? T A
EQUATION
INL (V)
0
max { V 4 , V 3 }
V DD – 0.6V
V 4
V 3
0
0.3
G
V DD - 0.3 V DD
G G
V IN (V)
FIGURE 1-8:
Output Voltage INL with the
standard condition V REF = V SS = 0V.
? 2003 Microchip Technology Inc.
DS21117A-page 7
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